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INTEGRATED CIRCUITS
DATA SHEET
TDA9853H I2C-bus controlled economic BTSC stereo decoder and audio processor
Product specification File under Integrated Circuits, IC02 2000 Dec 11
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
FEATURES * Voltage Controlled Amplifier (VCA) noise reduction circuit * Stereo or mono selectable at the AF outputs * Stereo pilot PLL circuit with ceramic resonator * Automatic pilot cancellation * I2C-bus transceiver. Audio processor * Selector for internal and external signals (line in) * Automatic Volume Level (AVL) control (control range +6 to -15 dB) * Volume control (control range +12 to -63 dB) * Mute control via I2C-bus * 4 fixed tone settings. ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION GENERAL DESCRIPTION
TDA9853H
The TDA9853H is a bipolar-integrated BTSC stereo decoder and audio processor for application in TV sets, VCRs and multimedia PCs.
VERSION SOT205-1
TDA9853H QFP44 plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
2000 Dec 11
2
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
QUICK REFERENCE DATA SYMBOL VCC ICC Vo(rms) PARAMETER supply voltage supply current output voltage (RMS value) composite input voltage 250 mV (RMS) for 100% modulation L + R (25 kHz deviation); fmod = 300 Hz CONDITIONS MIN. 7.8 25 -
TDA9853H
TYP. 8 33 500
MAX. 9 45 -
UNIT V mA mV
csL,R THDL,R S/N
stereo channel separation L and R total harmonic distortion L and R
14% modulation; fL = 300 Hz; fR = 3 kHz 15 100% modulation L or R; fmod = 1 kHz -
20 0.2
- 1
dB %
signal-to-noise ratio at line out mono via I2C-bus; referenced to 500 mV and at AF output output signal; volume 0 dB CCIR 468-2 weighted; quasi peak 50 2 -15 -63 - referenced to linear position; fmod = 20 Hz referenced to linear position; fmod = 20 Hz referenced to linear position; fmod = 20 kHz referenced to linear position; fmod = 20 kHz 10 3.5 6 - 60 73 - - - 0 12 5 8 -1.5 - - - +6 +12 - - - - - dB dBA V dB dB dB dB dB dB dB DIN noise weighting filter (RMS value) -
VI, O(rms) AVL Gc Llinear Lbass(max) Lbass(min)
signal handling (RMS value) AVL control range volume control range linear tone control tone control with maximum bass tone control with minimum bass
THD < 0.5%
Ltreble(max) tone control with maximum treble Ltreble(min) tone control with minimum treble
2000 Dec 11
3
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C3 C4 C2 CP2 2 R1 Q1 C5 C6 C7 C8 C9 C10 C11 C12 CP1 3 CPH 42 CER 43 CMO 5 CSS 6 LOR 25 composite baseband input C1 COMP 4 STEREO DECODER L+R DEMATRIX AND MODE SELECT FDI 35 L-R
BLOCK DIAGRAM
Philips Semiconductors
External Input Right (EIR)
handbook, full pagewidth
I2C-bus controlled economic BTSC stereo decoder and audio processor
LIR 26
CAV 29 AUTOMATIC VOLUME AND LEVEL CONTROL
VAR 23
VIR 24
TC1R TC2R BCR 21 20 19
INPUT SELECT
VOLUME RIGHT CONTROL
TONE RIGHT CONTROL
18
OUTR
4
R2 R3
TDA9853H
FDO 33
DETECTOR AND VOLTAGE CONTROLLED AMPLIFIER
SUPPLY
FILTER AND REFERENCE
I2C-BUS TRANSCEIVER
VOLUME LEFT CONTROL
TONE LEFT CONTROL
16
OUTL
32 BPU
31 CW C21
30 TW C20
41
28
36
27
9
8
7 RFR
40 39 38 37
11 VAL
10 VIL C15
13
14
15
VCAP AGND Vref C19 C18
LOL LIL C17
TC1L TC2L BCL C14
MAD C23 C22 R4 SCL SDA C16 C13
VCC External Input Left (EIL)
DGND
MHB789
Product specification
TDA9853H
Fig.1 Block diagram.
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
TDA9853H
Component list Electrolytic capacitors 20%; foil capacitors 10%; resistors 5%; unless otherwise specified; see Fig.1. COMPONENT C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 R1 R2 R3 R4 Q1 2.2 F 220 nF 2.2 F 220 nF 2.2 F 2.2 F 2.2 F 4.7 F 2.2 F 3.3 nF 150 pF 56 nF 56 nF 150 pF 3.3 nF 2.2 F 2.2 F 100 F 100 F 10 F 1 F 4.7 nF 22 nF 3.3 k 15 k 1.3 k 100 k CSB503F58 CSB503JF958 radial leads alternative as SMD VALUE electrolytic foil electrolytic foil electrolytic electrolytic electrolytic electrolytic electrolytic foil foil foil foil foil foil electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic foil foil 63 V 63 V 16 V 16 V 63 V 63 V 63 V 63 V 63 V 63 V 10% 63 V 63 V TYPE 63 V REMARK
2000 Dec 11
5
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
PINNING SYMBOL PIN n.c. CP2 CP1 COMP CMO CSS RFR LIL LOL VIL VAL n.c. TC1L TC2L BCL OUTL n.c. OUTR BCR TC2R TC1R n.c. VAR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DESCRIPTION not connected connector 2 for pilot detector capacitor connector 1 for pilot detector capacitor composite input signal capacitor for DC-decoupling mono capacitor for DC-decoupling stereo resistor for filter reference line input; left channel line output; left channel volume control input; left channel AVL output; left channel not connected treble capacitor 1; left channel treble capacitor 2; left channel bass capacitor; left channel left channel output not connected right channel output bass capacitor; right channel treble capacitor 2; right channel treble capacitor 1; right channel not connected AVL output; right channel BPU FDO n.c. FDI AGND DGND SDA MAD SCL VCC CPH CER n.c. 32 33 34 35 36 37 38 39 40 41 42 43 44 CAV TW CW 29 30 31 SYMBOL PIN VIR LOR LIR Vref VCAP 24 25 26 27 28
TDA9853H
DESCRIPTION volume control input; right channel line output; right channel line input; right channel reference voltage (0.5VCC) capacitor for electronic filtering of supply capacitor for AVL capacitor timing capacitor for VCA and band-pass filter lower corner frequency band-pass filter upper corner frequency fixed de-emphasis output not connected fixed de-emphasis input analog ground digital ground serial data input/output programmable address bit (module address) serial clock input supply voltage capacitor for phase detector ceramic resonator not connected
2000 Dec 11
6
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
TDA9853H
37 DGND
36 AGND
39 MAD
43 CER
42 CPH
41 VCC
38 SDA
40 SCL
44 n.c.
handbook, full pagewidth
n.c. CP2 CP1 COMP CMO CSS RFR LIL LOL
1 2 3 4 5 6 7 8 9
34 n.c.
35 FDI
33 FDO 32 BPU 31 CW 30 TW 29 CAV
TDA9853H
28 VCAP 27 Vref 26 LIR 25 LOR 24 VIR 23 VAR
VIL 10 VAL 11
n.c. 12
TC1L 13
TC2L 14
BCL 15
OUTL 16
n.c. 17
OUTR 18
BCR 19
TC2R 20
TC1R 21
n.c. 22
MHB790
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION Stereo decoder The composite signal is fed into a pilot detector/pilot cancellation circuit and into the MPX demodulator. The main L + R signal passes a 75 s fixed de-emphasis filter and is fed into the dematrix circuit. The decoded sub-signal L - R is applied to the Volume Controlled Amplifier (VCA) circuit. To generate the pilot signal the stereo demodulator uses a PLL circuit including a ceramic resonator. Mode selection The L - R signal is fed via the internal VCA circuit to the dematrix/switching circuit. Mode selection is achieved via the I2C-bus (see Table 9). The dematrix outputs can be muted via the I2C-bus (see Table 14).
Automatic volume level control The automatic volume level stage controls its output voltage to a constant level of typically 200 mV (RMS) from an input voltage range between 0.1 to 1.1 V (RMS). The circuit adjusts variations in modulation during broadcasting and because of changes in the programme material; this function can be switched off. To avoid audible plops during the permanent operation of the AVL circuit a soft blending scheme has been applied between the different gain stages. A capacitor (4.7 F) at pin CAV determines the attack and decay time constants. In addition the ratio of attack and decay times can be changed via the I2C-bus. Integrated filters The filter functions necessary for stereo demodulation are provided on-chip using transconductor circuits. The filter frequencies are controlled by the filter reference circuit via the external resistor R4.
2000 Dec 11
7
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
Audio processor SELECTOR The selector enables the selection of either the internal line output signals LOR and LOL (dematrix output) or the external line input signals LIR and LIL (see Table 16). The input signal capability of the line inputs (LIR/LIL) is 2 V (RMS). The output of the selector is DC-coupled to the automatic volume level control circuit. VOLUME The volume control range is from +12 dB to -63 dB in steps of 1 dB and ends with a mute step (see Table 8). Balance control is achieved by the independent volume control of each channel. BASS FUNCTION A single external 56 nF capacitor for each channel in combination with a linear operational amplifier and internal resistors provides a bass range of +12 dB for high bass and +5 dB for low bass. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCC VSDA, VSCL Vn Tamb Tstg Ves supply voltage voltage at pins SDA and SCL referenced to GND voltage of all other pins to GND ambient temperature storage temperature electrostatic handling voltage note 1 note 2 Notes VCC 9 V VCC > 9 V PARAMETER CONDITIONS TREBLE FUNCTION
TDA9853H
Two external capacitors C15 = 3.3 nF and C14 = 150 pF for each channel in combination with a linear operational amplifier and internal resistors provide a treble range of +8 dB for high treble and -1.5 dB for low treble. MUTE The mute function can be activated independently with the last step of volume control at the left or right output. By setting the general mute bit GMU the audio outputs OUTL and OUTR are muted.
MIN. - -0.3 -0.3 0 -20 -65 -200
MAX. 9.5 +VCC +9 VCC +70 +150 +200
UNIT V V V V C C V
-2000 +2000 V
1. Machine model class B, equivalent to discharging a 200 pF capacitor through a 0 series resistor (`0 ' is actually 0.75 H + 10 ). 2. Human body model class B, equivalent to discharging a 100 pF capacitor through a 1500 series resistor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 70 UNIT K/W
2000 Dec 11
8
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
TDA9853H
CHARACTERISTICS All voltages are measured relative to GND; VCC = 8 V; Rs = 600 ; AC-coupled; RL = 10 k; CL = 2.5 nF; fmod = 1 kHz mono signal; composite input voltage 250 mV (RMS) for 100% modulation L + R (25 kHz deviation); pilot 50 mV (RMS); Gv = 0 dB; linear tone control; AVL off; Tamb = 25 C; see Fig.1; unless otherwise specified. SYMBOL Supplies VCC ICC Vref Input stage Vi(max)(rms) Zi HR Vpil(rms) Vth(on)(rms) Vth(off)(rms) hys Vo(rms) cs(L,R) THDL,R S/N maximum input voltage (RMS value) input impedance 2 20 - 25 - 50 - - 2.5 500 20 0.2 - 32 - - 35 - - - - 1 V k supply voltage supply current internal reference voltage at pin Vref 7.8 25 8 33 9 45 V mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
0.45VCC 0.5VCC
0.55VCC V
Stereo decoder headroom for L + R, L and R nominal stereo pilot voltage (RMS value) pilot threshold voltage, stereo on (RMS value) pilot threshold voltage, stereo off (RMS value) hysteresis output voltage (RMS value) stereo channel separation L and R total harmonic distortion L and R signal-to-noise ratio at line output and AF output 100% modulation L + R; fmod = 300 Hz 14% modulation; fL = 300 Hz; fR = 3 kHz 100% modulation L or R; fmod = 1 kHz mono via I2C-bus; referenced to 500 mV output signal CCIR 468-2 weighted; quasi peak DIN noise weighting filter (RMS value) mute mute attenuation at LOL, LOR, 100% modulation L + R; VAL and VAR fmod = 300 Hz; mute via bit E6 nominal VCXO output frequency (32fH) spread of free-running frequency capture range frequency with nominal ceramic resonator with nominal ceramic resonator nominal pilot 50 - 63 60 73 - - - - dB dBA dB fmod = 300 Hz; THD < 15% 9 - - 15 - - 15 - dB mV mV mV dB mV dB %
Stereo decoder, oscillator (VCXO); note 1 fo ffr fcr - 500 190 503.5 - 265 - 507 - kHz kHz Hz
2000 Dec 11
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Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9853H
MAX.
UNIT
Audio control part; input pins VIL and VIR to pins OUTL and OUTR VO Zi Zo RL CL Vi(max)(rms) THD Vno DC output voltage volume input impedance output impedance output load resistance output load capacitance maximum input voltage (RMS value) total harmonic distortion noise output voltage THD < 0.5% 1 V (RMS) input voltage CCIR 468-2 weighted; quasi peak Gv = 10 dB Gv = 0 dB mute position Gc Gstep volume control range step resolution step error between adjoining step Ga GL m VDC(OS) attenuator set error gain tracking error mute attenuation DC step offset between any adjacent step DC step offset between any step to mute Tone control part Llinear Lbass(max) Lbass(min) Ltreble(max) Ltreble(min) linear tone control tone control with maximum bass tone control with minimum bass tone control with maximum treble tone control with minimum treble referenced to linear position; fmod = 20 Hz referenced to linear position; fmod = 20 Hz referenced to linear position; fmod = 20 kHz referenced to linear position; fmod = 20 kHz - 10 3.5 6 - 0 12 5 8 -1.5 - - - - - dB dB dB dB dB Gv = +12 to 0 dB Gv = 0 to -63 dB Gv = +12 to 0 dB Gv = -1 to -63 dB Gv = +12 to -15 dB and Gv = -16 to -63 dB; note 2 Gv = +12 to -50 dB Gv = -51 to -63 dB Gv = +12 to -50 dB maximum boost maximum attenuation - - - - - - - - - - 80 - - - - 110 33 10 12 63 1 - - - - - 0.2 - 2 1 220 50 - - - - 0.5 2 3 2 - 10 5 15 10 V V V dB dB dB dB dB dB dB dB mV mV mV mV 0.45VCC 0.5VCC 25 - 5 0 tbf - 30 80 - - 2 0.05 0.55VCC V 38 120 - 2.5 - - k k nF V %
2000 Dec 11
10
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
SYMBOL VCA Is nominal timing current for nominal release rate of VCA detector nominal detector release rate Is can be measured at pin TW via current meter connected to 0.5VCC + 1 V nominal timing current and external capacitor values 6.5 8 PARAMETER CONDITIONS MIN. TYP.
TDA9853H
MAX.
UNIT A
9.5
Relrate
-
125
-
dB/s
Automatic volume level control Gv Gstep voltage gain equivalent step width between the input stages (soft switching system) input voltage (RMS value) output voltage in AVL operation (RMS value) DC offset voltage between different gain steps maximum boost; note 3 maximum attenuation; note 3 Vo(AVL)(rms) Voffset(DC) maximum boost; note 3 maximum attenuation; note 3 5 14 - 6 15 1.5 7 16 - dB dB dB
Vi(rms)
- - 160
0.1 1.125 200 -
- - 250 20
V V mV mV
voltage at pin CAV - 6 to 5.83 V or 5.83 to 5.61 V or 5.61 to 4.83 V or 4.83 to 2.1 V; note 4 AT1 = 0; AT2 = 0; note 5 AT1 = 1; AT2 = 0; note 5 AT1 = 0; AT2 = 1; note 5 AT1 = 1; AT2 = 1; note 5 340 590 0.96 1.7 -
Ratt
discharge resistors for attack time constant
420 730 1.2 2.1 2 30
520 910 1.5 2.6 2.4 -
k k A A
Idec
charge current for decay time
normal mode; CCD = 0; note 6 1.6 Power-on speed-up; CCD = 1; note 6
Selector internal and external Zi s Vi(max)(rms) Gv Vo(rms) HRo Zo VO RL CL 2000 Dec 11 input impedance input isolation of one selected source to the other input maximum input voltage (RMS value) voltage gain, selector Vi = 1 V; fi = 1 kHz Vi = 1 V; fi = 12.5 kHz THD < 0.5% 16 70 70 - - 100% modulation - 9 - 5 - 11 20 76 76 2 0 25 - - - - - - 120 - 2.5 k dB dB V dB
Line output; pins LOL and LOR nominal output voltage (RMS value) output headroom output impedance DC output voltage output load resistance output load capacitance 500 - 80 - - mV dB k nF
0.45VCC 0.5VCC
0.55VCC V
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
SYMBOL PARAMETER CONDITIONS - 5 with 100 in series - - MIN. TYP.
TDA9853H
MAX. - - 2.5
UNIT
Monitor output; pins VAL and VAR VO RL CL VCC DC output voltage output load resistance output load capacitance 0.5VCC - - V k nF
Muting at power supply voltage drop for OUTR and OUTL supply voltage drop for mute active VCAP - 0.7 - V
Power-on reset; note 7 VPOR(start) VPOR(end) Digital part VIH VIL IIH IIL VOL Notes 1. The oscillator is designed to operate together with Murata resonator CSB503F58 or CSB503JF958 as SMD. Change of the resonator supplier is possible, but the resonator specification must be close to the specified ones. 2. 1.5 dB step error between -15 and -16 dB. 3. The AVL input voltage is internal. It corresponds to the output voltage OUTL and OUTR at AVL off. 4. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, -6 dB and -15 dB. 5. Attack time constant = CCAV x Ratt with CCAV = C8 (see Fig.1).
--------- ---------20 20 - 10 C CAV x 0.76 V 10 Decay time = -------------------------------------------------------------------------------I dec -G1 -G2
start of reset voltage end of reset voltage (I2C-bus pins); note 8
increasing supply voltage decreasing supply voltage increasing supply voltage
- - -
- tbf tbf - - - - -
2.5 - - VCC(9) +1.5 +10 +10 0.4
V V V
HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current LOW-level output voltage IIL = 3 mA
3 -0.3 -10 -10 -
V V A A V
6.
a) Example: CCAV = 4.7 F; Idec = 2 A; G1 = -9 dB; G2 = +6 dB decay time results in 4.14 s. 7. When reset is active the GMU bit (mute) is set and the I2C-bus receiver is in the reset position. 8. The AC characteristics are in accordance with the I2C-bus specification for standard mode (clock frequency maximum 100 kHz). A higher frequency, up to 280 kHz, can be used if all clock and data times are interpolated between standard mode (100 kHz) and fast mode (400 kHz) in accordance with the I2C-bus specification. Information about the I2C-bus can be found in brochure "I2C-bus and how to use it" (order number 9398 393 40011). 9. Maximum 9 V if VCC > 9 V.
2000 Dec 11
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Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
TDA9853H
handbook, full pagewidth
12
MHB791
gain (dB)
(1)
8
(2)
(3)
4
0
(4)
-4 10
102
103
104
f (Hz)
105
(1) (2) (3) (4)
Maximum bass. Maximum treble. Minimum bass. Minimum treble.
Fig.3 Tone control.
2000 Dec 11
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Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
I2C-BUS PROTOCOL I2C-bus format to read (slave transmits data) S Table 1 SLAVE ADDRESS R/W A DATA
TDA9853H
AN
P
Explanation of I2C-bus format to read (slave transmits data) NAME DESCRIPTION START condition; generated by the master 1011011; pin MAD not connected 1011010; pin MAD connected to ground logic 1 (read); generated by the master acknowledge; generated by the slave slave transmits an 8-bit data word acknowledge not; generated by the master STOP condition; generated by the master Definition of the transmitted bytes after read condition LSB D6 Y Bit functions of Table 2 BIT FUNCTION stereo pilot identification (stereo received = 1) Power-on reset; if PONR = 1, then Power-on reset is detected indefinite D5 Y D4 Y D3 Y D2 Y D1 PONR D0 STP
S Standard SLAVE ADDRESS (MAD) Pin programmable SLAVE ADDRESS R/W A DATA AN P Table 2
MSB D7 Y Table 3
STP PONR Y
I2C-bus format to write (slave receives data) S Table 4 SLAVE ADDRESS R/W A SUBADDRESS A DATA A P
Explanation of I2C-bus format to write (slave receives data) NAME DESCRIPTION START condition 101 101 1; pin MAD not connected 101 101 0; pin MAD connected to ground logic 0 (write) acknowledge; generated by the slave see Table 5 see Table 6 STOP condition
S Standard SLAVE ADDRESS Pin programmable SLAVE ADDRESS R/W A SUBADDRESS (SAD) DATA P
2000 Dec 11
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Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
TDA9853H
If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of Table 5 is performed. Table 5 Subaddress definition (second byte after slave address) MSB FUNCTION D7 Volume right Volume left Control 1 Control 2 Note 1. Significant subaddress bits. Table 6 Data definition (third byte after slave address) MSB FUNCTION D7 Volume right Volume left Control 1 Control 2 Table 7 0 0 0 0 D6 B6 C6 E6 0 D5 B5 C5 E5 0 D4 B4 C4 E4 F4 D3 B3 C3 E3 F3 D2 B2 C2 E2 F2 D1 B1 C1 E1 F1 D0 B0 C0 E0 F0 LSB 0 0 0 0 D6 0 0 0 0 D5 0 0 0 0 D4 0 0 0 0 D3 0 0 0 0 D2 0 0 0 0 D1(1) 0 0 1 1 LSB D0(1) 0 1 0 1
Bit functions of Table 6 SYMBOL VR0 to VR6 VL0 to VL6 STEREO GMU AVLON CCD AT1 and AT2 LMU TONE MODE MONO LITO volume control right volume control left mode selection for line out mute control for OUTL and OUTR AVL on/off increased AVL decay current on/off attack time at AVL line out mute on/off selection between four fixed tone controls selection between intern and extern forced mono on/off at OUTL and OUTR linear tone control on/off FUNCTION
BITS B0 to B6 C0 to C6 E0 E1 E2 E3 E4 and E5 E6 F0 and F1 F2 F3 F4
2000 Dec 11
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Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
Table 8 Volume setting DATA V6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 V5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 V4 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 V3 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 V2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 V1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
TDA9853H
FUNCTION Gv (dB) 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25
V0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
2000 Dec 11
16
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
FUNCTION Gv (dB) -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 -56 -57 -58 -59 -60 -61 -62 -63 Mute DATA V6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 V4 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 V3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 V2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 V1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
TDA9853H
V0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
2000 Dec 11
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Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
Table 9 Mode setting READABLE BIT SETTING BIT D0/STP E0/STEREO logic 1 (stereo received) logic 1 (stereo received) logic 0 (no stereo received) logic 0 (no stereo received) 1 0 Table 15 Tone setting 1 0 FUNCTION TONE Maximum bass and maximum treble DATA E1 1 0 Table 16 Selector setting Table 11 AVLON bit setting FUNCTION AVL Automatic volume control on Automatic volume control off Table 12 CCD bit setting FUNCTION AVL CURRENT Increased load current Load current for normal AVL decay time DATA E3 1 0 Table 18 Linear setting Table 13 AVL attack time; see Chapter "Characteristics" note 5 FUNCTION Ratt () 420 730 1200 2100 E5 0 0 1 1 DATA E4 0 1 0 1 Linear Tone FUNCTION MODE TONE DATA E2 1 0 Table 17 Mono setting FUNCTION MONO AT OUTL AND OUTR Forced mono No forced mono FUNCTION MODE INTERNAL/EXTERNAL External left and right Internal left and right Maximum bass and minimum treble Minimum bass and maximum treble Minimum bass and minimum treble F1 1 1 0 0 Table 14 Line out mute setting FUNCTION MUTE LINE OUTPUT Line output mute Line output active
TDA9853H
FUNCTION MODE LOL Left Mono Mono Mono LOR right mono mono mono
DATA E6 1 0
DATA F0 1 0 1 0
Table 10 Mute setting FUNCTION MUTE CONTROL FOR OUTR AND OUTL Forced mute at OUTR and OUTL No forced mute at OUTR and OUTL
DATA F2 1 0
DATA F3 1 0
DATA F4 1 0
2000 Dec 11
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Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
INTERNAL PIN CONFIGURATIONS
TDA9853H
+
2 3
+
8.5 k
12 k
3.5 k
MHB793
MHB792
Fig.4 Pin 2: CP2.
Fig.5 Pin 3: CP1.
4
+
25 k 25 k
5, 6
+
10 k 10 k
MHB795
50 pF 25 k 100 pF
MHB794
Fig.6 Pin 4: COMP.
Fig.7 Pin 5: CMO; pin 6: CSS.
8, 26 +
4V
1 k
+
20 k
MHB796
7
MHB797
Fig.8 Pin 7: RFR.
Fig.9 Pin 8: LIL; pin 26: LIR.
2000 Dec 11
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Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
TDA9853H
4 V 10, 24
+
9, 25
4V + 30 k
4V
MHB798
MHB799
Fig.10 Pin 9: LOL; pin 25: LOR.
Fig.11 Pin 10: VIL; pin 24: VIR.
+
11, 23 4 V 4V 80 5.4 k 13, 14 20, 21 + +
12 k
MHB801 MHB800
Fig.12 Pin 11: VAL; pin 23: VAR.
Fig.13 Pin 13: TC1L; pin 14: TC2L; pin 20: TC2R; pin 21: TC1R.
2000 Dec 11
20
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
TDA9853H
4 V 15, 19 + 28.5 k
+
16, 18
80
9.5 k
4V
MHB803
MHB802
Fig.14 Pin 15: BCL; pin 19: BCR.
Fig.15 Pin 16: OUTL; pin 18: OUTR.
27
+
28
3.4 k
4.7 k 300
3.4 k
5 k
MHB805 MHB804
Fig.16 Pin 27: Vref.
Fig.17 Pin 28: VCAP.
29
30
+
+
MHB806
MHB807
Fig.18 Pin 29: CAV.
Fig.19 Pin 30: TW.
2000 Dec 11
21
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
TDA9853H
+
31
35
+
+
6 k 16 k 32
MHB808 MHB809
Fig.20 Pin 31: CW.
Fig.21 Pin 32: BPU; pin 35: FDI.
38 33 1.8 k
+
MHB810 MHB811
Fig.22 Pin 33: FDO.
Fig.23 Pin 38: SDA.
5 V 40 39 + 1.8 k
1.8 k
MHB812 MHB813
Fig.24 Pin 39: MAD (I2C-bus address switch).
Fig.25 Pin 40: SCL.
2000 Dec 11
22
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
TDA9853H
42 41
4V
+
+
MHB814
10 k
10 k
MHB815
Fig.26 Pin 41: VCC.
Fig.27 Pin 42: CPH.
43
+
3 k
MHB816
Fig.28 Pin 43: CER.
2000 Dec 11
23
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
TDA9853H
SOT205-1
c
y X
33 34
23 22 ZE
A
e E HE wM bp pin 1 index 44 1 11 ZD bp D HD wM B vM B 12 detail X L Lp A A2 A1 (A 3)
e
vM A
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.60 A1 0.25 0.05 A2 2.3 2.1 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 14.1 13.9 E (1) 14.1 13.9 e 1 HD 19.2 18.2 HE 19.2 18.2 L 2.35 Lp 2.0 1.2 v 0.3 w 0.15 y 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT205-1 REFERENCES IEC 133E01 JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-08-01 99-12-27
2000 Dec 11
24
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
TDA9853H
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2000 Dec 11
25
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
Suitability of surface mount IC packages for wave and reflow soldering methods
TDA9853H
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2000 Dec 11
26
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo decoder and audio processor
DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
TDA9853H
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. PURCHASE OF PHILIPS I2C COMPONENTS DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2000 Dec 11
27
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260, Tel. +66 2 361 7910, Fax. +66 2 398 3447 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 70
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/01/pp28
Date of release: 2000
Dec 11
Document order number:
9397 750 07474

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